COM90C66 datasheet(33/76 Pages) SMSC

33 / 76 page

Transmit Command Chaining

When the processor issues the first ENABLE

TRANSMIT

PAGE

command,

the

COM90C66 responds in the usual manner by

resetting the TA and TMA bits to prepare for the

transmission from the specified page. The TA bit

can be used to see if there is currently a

transmission pending, but the TA bit is really

meant to be used in the non-chaining mode only.

The TTA bits provide the relevant information of

the device in the Command Chaining mode.

In the Command Chaining Mode, at any time

after the first command is issued, the processor

can issue a second ENABLE TRANSMIT FROM

PAGE nn command. The COM90C66 stores the

fact that the second transmit command was

issued, along with the page number.

After the first transmission is completed, the

COM90C66 updates the Status Register by

setting the TTA bit, which generates an interrupt.

The interrupt service routine will read the Status

to be a logic "1" and the TMA (Transmit Message

Acknowledge) bit will tell the processor whether

the transmission was successful. After reading

the Status Register, the CLEAR TRANSMIT

INTERRUPT command is issued, thus resetting

the TTA bit and clearing the interrupt. Note that

only

the

CLEAR

TRANSMIT

INTERRUPT

command will clear the TTA bit and the interrupt.

It is not necessary, however, to clear the bit or

the interrupt right away because the status of the

transmit operation is double buffered in order to

retain the results of the first transmission for

analysis by the processor. This information will

remain in the Status Register until the CLEAR

TRANSMIT INTERRUPT command is issued.

Note that the interrupt will remain active until the

command is issued, and the second interrupt will

not occur until the first interrupt is cleared. The

TMA bit is also double buffered to reflect whether

the appropriate transmission was a success.

The TMA bit should only be considered valid

after the corresponding TTA bit has been set to a

logic "1". The TMA bit never causes an interrupt.

When the token is received again, the second

transmission will be automatically initiated after

the first is completed by using the stored

ENABLE TRANSMIT FROM PAGE nn command.

The operation is as if a new ENABLE TRANSMIT

FROM PAGE nn command has just been issued.

After the first Transmit status bits are cleared,

the Status Register will again be updated with the

results of the second transmission and a second

interrupt resulting from the second transmission

will occur.

The COM90C66 guarantees a

minimum of 200nS interrupt inactive time interval

before the following edge.

The Transmitter Available (TA) bit of the Interrupt

Mask Register now masks only the TTA bit of the

Status Register, not the TA bit as in the non-

chaining mode.

Since the TTA bit is only set

upon transmission of a packet (not by RESET),

and since the TTA bit may easily be set by

issuing

CLEAR

TRANSMIT

INTERRUPT

command, there is no need to use the TA bit of

the Interrupt Mask Register to mask interrupts

generated by the TTA bit of the Status Register.

In both the Command Chaining mode and the

non-chaining

mode,

the

DISABLE

TRANSMITTER command will cancel the oldest

transmission. This permits canceling a packet

destined for a node not ready to receive. If both

packets should be canceled, two DISABLE

TRANSMITTER commands should be issued.

Receive Command Chaining

Like the Transmit Command Chaining operation,

the

processor

can

issue

two

consecutive

ENABLE RECEIVE FROM PAGE nn commands.

After the first packet is received into the first

specified page, the TRI bit of the Status Register

will be set to logic "1", causing an interrupt.

Again,

the

interrupt

need

not

serviced

COM90C66 Datasheet(PDF) 33 Page - SMSC Corporation

COM90C66 Datasheet(HTML) 33 Page - SMSC Corporation

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