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COM90C66 Datasheet(PDF) 36 Page - SMSC Corporation

Part # COM90C66
Description  ARCNET Controller/Transceiver with AT Interface and On-Chip RAM
PDF  76 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM90C66 Datasheet(HTML) 36 Page - SMSC Corporation

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36
FIGURE 10 - INTERNAL RESET SEQUENCE
Hardware or
Software Reset
Internal POR
nMEMR, nMEMW,
nIOR, nIOW
Microsequencer POR
Internal Reset
102.4 uS or
256 bit clocks
12 uS
Cycles
Enabled
1
2
3
1
During this time, the microsequencer is being reset and the transmitter
portion of the device is disabled.
During this time, the nTOPH, nTOPL, nPROM, nIOCS16, and nMEMCS16 signals are a
a logic "1"; the INTR signal is a logic "0"; the data bus is in the high
impedance state; and the IOCHRDY signal is in normal operation.
The 2nd cycle should be
issued after the 12uS.
2
During this time, the microsequencer writes D1H to address 00H, and the Node
3
ID number to 01H. The transmitter portion of the device is enabled.



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