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COM90C66 Datasheet(PDF) 49 Page - SMSC Corporation

Part # COM90C66
Description  ARCNET Controller/Transceiver with AT Interface and On-Chip RAM
PDF  76 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM90C66 Datasheet(HTML) 49 Page - SMSC Corporation

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49
TIMING DIAGRAMS
The AC parameters in Figures 14-26 are preliminary. Enhancements will follow.
FIGURE 14 - ZERO WAIT STATE AND IOCHRDY TIMING
nMEMR,
nMEMW,
nIOR, or
nIOW
nOWS**
IOCHRDY**
t1
t2
t3
t4
t5
20
t1
t2
t3
t4
t5
Parameter
Control Signal Pulse Width
Control Signal Low to nOWS Low
Control Signal High to nOWS High
Control Signal Low to IOCHRDY Low
IOCHRDY Low Pulse Width
min
80
0
0
50
typ
max
20
115
units
nS
nS
nS
nS
nS
20
0
** These signals are mutually exclusive. Only one signal is active on any given board, depending
on the WAIT STATE bit of the Configuration Register.
*
* 1.2 uS for back-to-back 8-bit cycles
2.5 uS for 16-bit cycles
t5
50
115



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