COM90C66 datasheet(64/76 Pages) SMSC

64 / 76 page

ADDENDUM 2

DATA SHEET ERRATA FOR REVISION D COM90C66

The Revision D device contains 16-bit detection circuitry on the input of pin 60 to allow the device

to power up in 16-bit mode.

If pin 60 senses a low level any time between hardware reset and

writing to the Configuration Register, the device defaults to 16-bit mode.

If a low level is not

sensed on pin 60, the device defaults to 8-bit mode. The mode may be overridden via software, if

desired.

In the generation of the nMEMCS16 signal, the Revision D device decodes the A19-A11 addresses

before they are latched by the device. The earlier comparison allows the nMEMCS16 signal to be

activated and deactivated more quickly by being independent of the BALE signal.

In the generation of the nIOCS16 signal, the Revision D device decodes the A15-A2 addresses

before they are latched by the device. The earlier comparison allows the nIOCS16 signal to be

activated and deactivated more quickly by being independent of the BALE signal.

In the Revision D device, when the IOCHRDY signal is negated for internal accesses, it is always

negated for two to three XTAL1 clock periods rather than one to two.

In the Revision D device, the leading edges of the nMEMR and nMEMW signals internally latch

the addresses. When the device is used in 8-bit mode, the BALE signal should be tied high. In

this case, the 16-bit cycles which get broken into two 8-bit cycles will now be addressed properly

for both cycles because the ALE signal is no longer depended upon.

Any reference to the

requirement of the ALE signal should be disregarded.

These corrections apply to this data sheet only when used for Revision D of the COM90C66. This

COM90C66 revision is identified on the part by either the letter "D" preceding the date code or no letter

at all preceding the date code.

Specific entries in table format appear on the following pages.

COM90C66 Datasheet(PDF) 64 Page - SMSC Corporation