Memory Management Unit
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
6-19
6.12 Fault address and fault status registers
Aborts resulting from data accesses, Data Aborts are acted upon by the CPU
immediately, and the MMU places an encoded 4-bit value FS[3:0], along with the 4-bit
encoded domain number, in the FSR.
In addition, the virtual processor address which caused the data abort is latched into the
FAR. If an access violation simultaneously generates more than one source of abort,
they are encoded in the priority listed in Table 6-5.
Note
Any abort masked by the priority encoding can be regenerated by fixing the primary
abort and restarting the instruction.
CPU instructions are prefetched, so a Prefetch Abort simply flags the instruction as it
enters the instruction pipeline. Only when, and if, the instruction is executed does it
cause an abort. An abort is not acted upon if the instruction is not used, that is, it is
Table 6-5 Priority encoding of fault status
Priority
Source
FS[3:0]
Domain
[3:0]
FAR
Highest
Alignment
00x1a
Invalid
Valid
Bus error (translation) level 1
Level 2
1100
1110
Invalid
Valid
Valid
Valid
Translation section
Page
0101
0111
Invalid
Valid
Valid
Valid
Domain section
Page
1001
1011
Valid
Valid
Valid
Valid
Permission section
Page
1101
1111
Valid
Valid
Valid
Valid
Bus error (linefetch) section
Page
0100
0110
Valid
Valid
Contains the address of the start of the linefetch
Contains the address of the start of the linefetch
Lowest
Bus error (other) section
Page
1000
1010
Valid
Valid
Valid
Valid
a.
x is undefined, and can be read as zero or one.
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