Introduction
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
1-9
Logical
Test
TST{cond} Rn, <Oprnd2>
Test equivalence
TEQ{cond} Rn, <Oprnd2>
AND
AND{cond}{S} Rd, Rn, <Oprnd2>
EOR
EOR{cond}{S} Rd, Rn, <Oprnd2>
ORR
ORR{cond}{S} Rd, Rn, <Oprnd2>
Bit clear
BIC{cond}{S} Rd, Rn, <Oprnd2>
Branch
Branch
B{cond} label
Branch with link
BL{cond} label
Branch, and exchange
instruction set
BX{cond} Rn
Load
Word
LDR{cond} Rd, <a_mode2>
Word with User Mode privilege
LDR{cond}T Rd, <a_mode2P>
Byte
LDR{cond}B Rd, <a_mode2>
Byte with User Mode privilege
LDR{cond}BT Rd, <a_mode2P>
Byte signed
LDR{cond}SB Rd, <a_mode3>
Halfword
LDR{cond}H Rd, <a_mode3>
Halfword signed
LDR{cond}SH Rd, <a_mode3>
Multiple
Block data operations
Increment before
LDM{cond}IB Rd{!}, <reglist>{^}
Increment after
LDM{cond}IA Rd{!}, <reglist>{^}
Decrement before
LDM{cond}DB Rd{!}, <reglist>{^}
Decrement after
LDM{cond}DA Rd{!}, <reglist>{^}
Stack operations
LDM{cond}<a_mode4L> Rd{!}, <reglist>
Stack operations, and restore
CPSR
LDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^
Table 1-2 ARM instruction summary (continued)
Operation
Assembler
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