ARM720T datasheet(23/242 Pages) ETC2

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Introduction

ARM DDI 0192A

1-7

Figure 1-2 ARM instruction set formats

Note

Some instruction codes are not defined but do not cause the Undefined instruction trap

to be taken. For example, a multiply instruction with bit 6 changed to a 1. You must not

use these instructions, as their action might change in future ARM implementations.

Data processing

immediate

Multiply long

Load/store halfword/

signed byte

Load/store halfword/

signed byte

Load/store multiple

Branch and branch with

link

Coprocessor load and

store

Coprocessor data

processing

Coprocessor register

transfers

Software interrupt

P U S W L

Multiply

0 0 0 0 0 0 A S

24_bit_offset

RdHi

U N W L

op1

swi_number

RdLo

CRn

CRd

cp_num

1 0 0 1

SBZ

1 S H 1

High offset 1 S H 1

Low offset

8_bit_offset

op2

CRm

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Data processing

immediate shift

0 0 0

opcode

shift immediate shift 0

Data processing register

shift

0 0 0

opcode

shift 1

Move from status register

0 0 0 1 0 R 0 0

SBO

SBZ

Move immediate to status

0 0 1 1 0 R 1 0

Mask

SBO

rotate

immediate

Move register to status

0 0 0 1 0 R 1 0

Mask

SBO

SBZ

Branch/exchange

instruction set

0 0 0 1 0 0 1 0

SBO

0 0 0

Load/store immediate

offset

0 1 0 P U B W L

immediate

Load/store register offset

0 1 1 P U B W L

shift immediate shift 0

Swap/swap byte

0 0 0 1 0 B 0 0

1 0 0 1

SBZ

Undefined

cond

0 0 1

rotate

immediate

cond

0 1 1 x

x x x x x x x x x x x x x x x x x x x

x x x x

cond

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