ARM720T datasheet(63/242 Pages) ETC2

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Configuration

ARM DDI 0192A

3-3

3.2

Internal coprocessor instructions

The ARM720T instruction set allows specialized additional instructions to be

implemented using coprocessors. These are separate processing units that are coupled

to the ARM720T processor.

Note

The CP15 register map might change in future ARM processors. You are strongly

recommended to structure software so that any code accessing CP15 is contained in a

single module. It can then be updated easily.

CP15 registers can only be accessed with MRC and MCR instructions in a privileged

mode. The instruction bit pattern of the MCR and MRC instructions is shown in Figure

3-1.

Figure 3-1 MRC and MCR bit pattern

CDP, LDC, and STC instructions, as well as unprivileged MRC and MCR instructions

to CP15 cause the Undefined Instruction trap to be taken.

The CRn field of MRC and MCR instructions specifies the coprocessor register to

access. The CRm field and opcode_2 fields specify a particular action when addressing

some registers.

In all instructions accessing CP15:

•

the opcode_1 field should be zero (SBZ).

•

the opcode_2 and CRm fields should be zero except when accessing registers 7,

8, and 13 when the specified values must be used to select the desired cache,

TLB, or process identifier operations.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

1 1 1

opcode_1

CRn

CRm

1 1 1 1 opcode_2 1

Cond

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