Configuration
3-2
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
3.1
About configuration
The operation and configuration of ARM720T is controlled:
•
directly using coprocessor instructions
•
indirectly using the MMU page tables.
The coprocessor instructions manipulate a number of on-chip registers which control
the configuration of the following:
•
cache
•
write buffer
•
MMU
•
other configuration options.
3.1.1
Compatibility
To ensure backwards compatibility of future CPUs:
•
all reserved or unused bits in registers and coprocessor instructions must be
programmed to 0
•
invalid registers must not be read or written
•
the following bits must be programmed to 0:
—
Register 1, bits[31:14] and bits [12:10]
—
Register 2, bits[13:0]
—
Register 5, bits[31:9]
—
Register 7, bits[31:0]
—
Register 13 FCSE PID, bits[24:0].
3.1.2
Notation
Throughout this section, the following terms and abbreviations are used:
Unpredictable (UNP)
If specified for reads, the data returned when reading from this
location is unpredictable. It can have any value.
If specified for writes, writing to this location causes
unpredictable behavior or change in device configuration.
Should Be Zero (SBZ)
When writing to this location, all bits of this field should be zero.
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