ARM720T datasheet(74/242 Pages) ETC2

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Instruction and Data Cache

4-2

ARM DDI 0192A

4.1

About the instruction and data cache

The cache only operates on a write-through basis with a read-miss allocation policy and

a random replacement algorithm.

4.1.1

IDC operation

The ARM720T contains an 8KB mixed Instruction and Data Cache (IDC).

The C bit in the ARM720T control register and the cachable bit in the MMU page tables

only affect loading data into the cache. The cache is always searched regardless of these

two bits. If the data is found then it is used, so when the cache is disabled, it must also

be flushed.

The IDC has 512 lines of 16 bytes (four words), arranged as a 4-way set-associative

cache, and uses the virtual addresses generated by the processor core after relocation by

the FCSE PID as appropriate. The IDC is always reloaded a line at a time (four words).

It can be enabled or disabled using the ARM720T control register and is disabled on

BnRES.

The operation of the cache is further controlled by the Cachable bit (C bit) stored in the

MMU page table (see Chapter 6 Memory Management Unit). For this reason, the MMU

must be enabled in order to use the IDC. However, the two functions can be enabled

simultaneously, with a single write to the control register.

4.1.2

Cachable bit

The C bit determines whether data being read can be placed in the IDC and used for

subsequent read operations. Typically, main memory is marked as cachable to improve

system performance, and I/O space is marked as noncachable to stop the data being

stored in the ARM720T cache.

For example, if the processor is polling a hardware flag in I/O space, it is important that

the processor is forced to read data from the external peripheral, and not a copy of the

initial data held in the cache. The cachable bit can be configured for both pages and

sections.

Cachable reads (C=1)

A line fetch of four words is performed when a cache miss occurs in a cachable area of

memory, and it is randomly placed in a cache bank.

Uncachable reads (C=0)

An external memory access is performed and the cache is not written.

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