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Programmer’s Model
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
2-17
2.8.2
Action on leaving an exception
On completion, the exception handler:
1.
Moves the LR, minus an offset where appropriate, to the PC. The offset varies
depending on the type of exception.
2.
Copies the SPSR back to the CPSR.
3.
Clears the interrupt disable flags, if they were set on entry.
Note
An explicit switch back to Thumb state is never necessary, because restoring the CPSR
from the SPSR automatically sets the T bit to the value it held immediately prior to the
exception.
2.8.3
Exception entry and exit summary
Table 2-3 summarizes the PC value preserved in the relevant R14 on exception entry,
and the recommended instruction for exiting the exception handler.
Table 2-3 Exception entry and exit
Exception
Return Instruction
Previous State
ARM R14_x
Thumb R14_x
BLa
a.Where PC is the address of the BL/SWI/Undefined Instruction fetch that had
the Prefetch Abort.
MOV PC, R14
PC + 4
PC + 2
SWIa
MOVS PC, R14_svc
PC + 4
PC + 2
UDEFa
MOVS PC, R14_und
PC + 4
PC + 2
FIQb
b.Where PC is the address of the instruction that was not executed because the
FIQ or IRQ took priority.
SUBS PC, R14_fiq, #4
PC + 4
PC + 4
IRQ b
SUBS PC, R14_irq, #4
PC + 4
PC + 4
PABTa
SUBS PC, R14_abt, #4
PC + 4
PC + 4
DABTc
SUBS PC, R14_abt, #8
PC + 8
PC + 8
RESETd
NA
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