ARM720T datasheet(54/242 Pages) ETC2

54 / 242 page

Programmer’s Model

2-18

ARM DDI 0192A

2.8.4

Fast interrupt request

The FIQ exception is designed to support a data transfer or channel process. In ARM

state it has sufficient private registers to remove the necessity for register saving,

minimizing the overhead of context switching.

FIQ is externally generated by taking the nFIQ input LOW. nFIQ and nIRQ are

considered asynchronous, and a cycle delay for synchronization is incurred before the

interrupt can affect the processor flow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ

handler must leave the interrupt by executing:

SUBS PC, R14_fiq, #4

FIQ can be disabled by setting the CPSR F flag.

Note

This is not possible from User mode. If the F flag is clear, ARM720T checks for a LOW

level on the output of the FIQ synchronizer at the end of each instruction.

2.8.5

Interrupt request

The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input.

IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered.

It can be disabled at any time by setting the I bit in the CPSR, though this can only be

done from a privileged (non-User) mode.

Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ

handler must return from the interrupt by executing:

SUBS PC, R14_irq, #4

2.8.6

Abort

An abort indicates that the current memory access cannot be completed. It can be

signaled either by the protection unit, or by the external BERROR input. The

ARM720T checks for the abort exception during memory access cycles.

There are two types of abort:

Prefetch Abort

This occurs during an instruction prefetch.

c.Where PC is the address of the Load or Store instruction that generated the

Data Abort.

d.The value saved in R14_svc upon reset is unpredictable.

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