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Programmer’s Model
2-20
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
2.8.8
Undefined instruction
When ARM720T comes across an instruction that it cannot handle, it takes the
undefined instruction trap. This mechanism can be used to extend either the Thumb or
ARM instruction set by software emulation.
After emulating the failed instruction, the trap handler must execute the following
irrespective of the state (ARM or Thumb):
MOVS PC, R14_und
This restores the CPSR and returns to the instruction following the Undefined
Instruction.
2.8.9
Exception vectors
The ARM720T can have exception vectors mapped to either low or high addresses,
controlled by the V bit in the control register (See Register 1, control register on
page 3-5). Table 2-4 lists the exception vector addresses.
Note
The low addresses are those generated by the processor core before relocation.
Table 2-4 Exception vector addresses
High address
Low address
Exception
Mode on entry
0xFFFF0000
0x00000000
Reset
Supervisor
0xFFFF0004
0x00000004
Undefined instruction
Undefined
0xFFFF0008
0x00000008
Software interrupt
Supervisor
0xFFFF000C
0x0000000C
Abort (prefetch)
Abort
0xFFFF0010
0x00000010
Abort (data)
Abort
0xFFFF0014
0x00000014
Reserved
Reserved
0xFFFF0018
0x00000018
IRQ
IRQ
0xFFFF001C
0x0000001C
FIQ
FIQ
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