77 / 242 page
Instruction and Data Cache
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
4-5
4.3
IDC enable, disable, and reset
The IDC is automatically disabled and flushed on BnRES. Once enabled, cachable read
accesses cause lines to be placed in the cache.
To enable the IDC:
1.
Make sure that the MMU is enabled first by setting bit 0 in the control register.
2.
Enable the IDC by setting bit 2 in the control register. The MMU and IDC can be
enabled simultaneously with a single write to the control register.
To disable the IDC:
1.
Clear bit 2 in the control register.
2.
Perform a flush by writing to the cache operations register.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
