ARM720T datasheet(87/242 Pages) ETC2

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Memory Management Unit

ARM DDI 0192A

6-5

6.3

Address translation process

The MMU translates virtual addresses generated by the CPU after relocation by the

FCSE PID into physical addresses to access external memory. It also derives and checks

the access permission. Translation information, that consists of both the address

translation data and the access permission data, resides in a translation table located in

physical memory.

The MMU provides the logic required to:

•

traverse this translation table

•

obtain the translated address

•

check the access permission.

There are three routes by which the address translation, and therefore permission check,

takes place. The route taken depends on whether the address has been marked as a

section-mapped access or a page-mapped access. There are two sizes of page-mapped

access, large pages and small pages. However, the translation process always starts out

in the same way, as described in Translation table base, with a level one fetch. A

section-mapped access only requires a level one fetch, but a page-mapped access also

requires a level two fetch.

6.3.1

Translation table base

The translation process is initiated when the TLB does not contain an entry for the

requested virtual address. The Translation Table Base (TTB) register points to the base

of a table in physical memory that contains:

•

section and page descriptors

•

section or page descriptors.

The 14 low-order bits of the TTB Register should be zero as illustrated in Figure 6-1.

Figure 6-1 Translation table base register

Note

The table must reside on a 16KB boundary.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Translation table base

SBZ

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