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Configuration
3-10
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
Two TLB operations are defined, and the function to be performed selected by the
opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8. This is
listed in Table 3-3.
Reading from CP15 register 8 is undefined.
The Invalidate TLB function invalidates all of the unlocked entries in the TLB.
The Invalidate TLB single entry function invalidates any TLB entry corresponding to
the Virtual Address given in Rd.
Note
Register 8 contains a modified virtual address if the FCSE PID register is nonzero.
3.3.10
Registers 9 to 12, reserved
Accessing any of these registers is undefined. Writing to any of these registers is
undefined.
3.3.11
Register 13, process identifier
Two independent process identifier registers can be accessed using register 13:
•
Fast context switch extension process identifier on page 3-11
•
Trace process identifier on page 3-11.
Table 3-3 TLB operations
Function
opcode_2 value
CRm value
Data
Instruction
Invalidate TLB
0b000
0b0111
SBZ
MCR
p15, 0, Rd, c8, c7, 0
Invalidate TLB
single entry
0b001
0b0111
Virtual Address
MCR
p15, 0, Rd, c8, c7, 1
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