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Programmer’s Model
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
2-23
2.10 Reset
When the BnRES signal goes LOW, ARM720T:
1.
Abandons the executing instruction.
2.
Flushes the cache and Translation Lookaside Buffer (TLB).
3.
Disables the Write Buffer (WB), cache, and MMU.
4.
Resets the FCSE PID.
5.
Continues to fetch instructions from incrementing word addresses.
When BnRES goes HIGH again, the ARM720T:
1.
Overwrites R14_svc and SPSR_svc by copying the current values of the PC and
CPSR into them. The value of the saved PC and SPSR is not defined.
2.
Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR,
and clears the CPSR T bit.
3.
Forces the PC to fetch the next instruction from the low reset exception vector.
4.
Resumes execution in ARM state.
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