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Memory Management Unit
6-6
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
6.3.2
Level 1 fetch
Bits [31:14] of the TTB register are concatenated with bits [31:20] of the virtual address
to produce a 30-bit address. This address selects a 4-byte translation table entry that is
a first level descriptor for either a section or a page. Bit 1 of the returned descriptor
specifies whether it is for a section or page. This is shown in Figure 6-2.
.
Figure 6-2 Accessing the translation table first level descriptors
31
20 19
00
Table index
Section index
31
14 13
00
Translation base
SBZ
31
14 13
02 01 00
Translation base
Table index
31
00
Virtual address
Translation table base
First level descriptor
0 0
18
12
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