7549 datasheet(40/73 Pages) RENESAS

40 / 73 page

Rev.2.00

Mar 05, 2007

Page 40 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

• Notes on Watchdog Timer

(1) The watchdog timer operates in wait mode. To prevent

underflow, write to the watchdog timer control register.

The watchdog timer stops in stop mode, but starts counting

at the same time as exiting stop mode. After exiting stop

mode, it continues counting during oscillation stabilization

time. To prevent underflow during the period, the watchdog

timer H count source selection bit (bit 7) in the watchdog

timer control register (address 003916) should be set to “0”

before executing the STP instruction.

Note that the watchdog timer continues counting even if the

STP instruction is executed in the following two conditions:

Stopping the low-speed on-chip oscillator: Disabled (bit

4 in FSROM2)

Source clock of the watchdog timer: Low-speed on-chip

oscillator/16 (bit 0 in FSROM2)

Stopping the low-speed on-chip oscillator: Disabled (bit

4 in FSROM2)

Source clock of the watchdog timer:

φSOURCE (bit 0 in

FSROM2)

φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in

CLKM)

(2) STP instruction function selection bit

The function of the STP instruction can be selected by the bit

2 in FSROM2. This bit cannot be used for rewriting by

executing the STP instruction.

• When this bit is set to “0”, stop mode is entered by

executing the STP instruction.

• When this bit is set to “1”, internal reset occurs by

executing the STP instruction.

7549 Datasheet(PDF) 40 Page - Renesas Technology Corp