UCS1002-3 datasheet(24/114 Pages) MICROCHIP

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UCS1002-3

DS20006852A-page 24

 2023 Microchip Technology Inc. and its subsidiaries

Figure 5-4 shows a system configuration in which the

UCS1002-3 provides a port power switch, low-power

Attach Detection, charger emulation (with no USB host)

and portable device attachment detected signaling.

This configuration is useful for wall adapter-type

applications.

FIGURE 5-4:

UCS1002-3 System Configuration (No SMBus, No USB Host, with Charger

Emulation).

UCS1002-3 references design is available;

contact your Microchip representative.

5.1

UCS1002-3 Power States

The UCS1002-3 has the following power states:

UCS1002

LATCH

ALERT#

PWR_EN

3 V – 5.5 V

GND

Device

DPIN

DMIN

DPOUT

DMOUT

VDD

5 V

VBUS1

VBUS2

VS1

VS2

COMM_SEL / ILIM

3 V – 5.5 V

Auto-recovery

Upon Fault

Latch

Upon Fault

EM_EN

SEL

A_DET#

5 V

CBUS

Disable Detect

State

Enable Detect

State

CIN

VDD

15 K

TABLE 5-1:

POWER STATES DESCRIPTION

State

Description

OFF

This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device

is considered OFF. The UCS1002-3 does not retain its digital states and register contents, nor respond to

SMBus/I2C communications. The port power switch, bypass switch, and the high-speed data switches

are turned OFF. See Section 5.1.1 “Off State Operation”.

Sleep

This is the lowest power state available. While in this state, the UCS1002-3 retains digital functionality,

respond to changes in emulation controls and wake to respond to SMBus/I2C communications. The high-

speed switch and all other functionality are disabled. See Section 5.1.2 “Sleep State Operation”.

Detect

This is a low-current power state. In this state, the device is actively looking for a portable device to be

attached. The high-speed switch is disabled by default. While in this state, the UCS1002-3 retains the

configuration and charge rationing data, but does not monitor the bus current. The SMBus/I2C

communications is fully functional. See Section 5.1.3 “Detect State Operation”.

Error

This power state is entered when a fault condition exists. See Section 5.1.5 “Error State Operation”.

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