UCS1002-3 datasheet(51/114 Pages) MICROCHIP

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DS20006852A-page 51

UCS1002-3

INTERRUPT STATUS REGISTER (ADDRESS 10h)

R/W-0

R-0

ERR

DISCHARGE

_ERR

RESET

MIN_

KEEP_OUT

TSD

OVER

_VOLT

BACK

_VOLT

OVER_LIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ERR: Indicates that an error is detected and the device has entered the Error state. Writing this bit to a ‘0’

clears the Error state and enables the device to return to the Active state. When written to ‘0’, all error

conditions are checked. If all error conditions are removed, the UCS1002-3 returns to the Active state. This

bit is automatically set by the UCS1002-3 when the Error state is entered. Regardless of the fault handling

mechanism used, if any other bit is set in the Interrupt Status register (10h), the device does not leave the

Error state. (Note 1 and Note 2)

This bit is automatically cleared by the UCS1002-3 if the Auto-Recovery Fault Handling functionality is active

and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is disabled.

1 = One or more errors are detected, and the UCS1002-3 has entered the Error state.

0 = There are no errors detected.

bit 6

DISCHARGE_ERR: Indicates that the UCS1002-3 is unable to discharge the VBUS node. This bit is

cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT#

pin to be asserted and the device to enter the Error state.

1 = UCS1002-3 is unable to discharge the VBUS node.

0 = No VBUS discharge error.

bit 5

RESET: Indicates that the UCS1002-3 is on reset and must be reprogrammed. This bit is set at power-up.

This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin is not asserted

when this bit is set. This data is retained in the Sleep state.

1 = UCS1002-3 is on reset.

0 = Reset did not occur.

bit 4

MIN_KEEP_OUT: Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN. This bit is

cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT#

pin to be asserted and the device to enter the Error state.

1 = VBUS < VBUS_MIN

0 = VBUS > VBUS_MIN

bit 3

TSD: Indicates that the internal temperature has exceeded TTSD threshold and the device has entered the

Error state. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This

bit causes the ALERT# pin to be asserted and the device to enter the Error state.

1 = Internal temperature > TTSD

0 = Internal temperature < TTSD

bit 2

OVER_VOLT: Indicates that the VS voltage has exceeded the VS_OV threshold and the device has entered

the Error state. This bit is cleared when read, if the error condition is removed or if the ERR bit is cleared.

This bit causes the ALERT# pin to be asserted and the device to enter the Error state.

1 = VS > VS_OV

0 = VS < VS_OV

bit 1

BACK_VOLT: Indicates that the VBUS voltage has exceeded the VS or VDD voltages by more than

150 mV. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit

causes the ALERT# pin to be asserted and the device to enter the Error state.

1 = VBUS > VS, or VBUS > VDD by more than 150 mV

0 = VBUS voltage did not exceed the VS and VDD voltages by more than 150 mV

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