UCS1002-3 datasheet(59/114 Pages) MICROCHIP

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DS20006852A-page 59

UCS1002-3

10.4.4

ATTACH DETECTION

CONFIGURATION REGISTER

The contents of this register are retained in Sleep.

bit 7

PIN_IGNORE: Ignores the M1, M2, PWR_EN, and EM_EN pin states when determining the Active

mode selection and power state.

1 = The Active mode selection and power state are set by the individual control bits and not by the

M1, M2, PWR_EN, and EM_EN pin states. These pin states are ignored.

0 = The Active mode selection and power state are set by the OR’d combination of the M1, M2,

PWR_EN, and EM_EN pin states and the corresponding bit states.

bit 6

Unimplemented

bit 5

EM_EN_SET: In conjunction with other controls, determines the Active mode that is selected (see

Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the

EM_EN pin.

bit 4

M2_SET: In conjunction with other controls, determines the Active mode that is selected (see

Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M2

pin.

bit 3

M1_SET: In conjunction with other controls, determines the Active mode that is selected (see

Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M1

pin.

bit 2

S0_SET: In SMBus mode, enables the Attach and Removal Detection feature and affects the power

state (see Section 9.2 “Active Mode Selection”).

1 = Detection is enabled. Also see Table 5-2.

0 = Detection is not enabled. Also see Table 5-2.

bit 1

PWR_EN_SET: Controls whether the port power switch may be turned ON or not and affects the

power state (see Section 5.3.4 “PWR_EN Input”). This bit is OR’d with the PWR_EN pin and the

polarity of both are controlled by SEL pin decode. Thus, if the polarity is set to active-high, either the

PWR_EN pin or this bit must be ‘1’ to enable the port power switch.

bit 0

LATCH_SET: In SMBus mode, controls the fault handling routine that is used in case an error is

detected (see Section 5.3.5 “Latch Input”).

1 = The UCS1002-3 latches its error conditions. In order for the device to return to normal Active

state, the ERR bit must be cleared by the user.

0 = The UCS1002-3 automatically retries when an error condition is detected.

R/W-0

R/W-1

R/W-0

R/W-1

RESERVED

DISCHG_TIME_SEL[1:0]

ATT_TH[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RESERVED: Do not change.This bit will read ‘0’ and must not be written to a logic ‘1’.

bit 6

RESERVED: Do not change. This bit will read ‘1’ and must not be written to a logic ‘0’.

bit 5-4

RESERVED: Do not change.These bits will read ‘0’ and must not be written to a logic ‘1’.

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