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UCS1002-3 Datasheet(PDF) 82 Page - Microchip Technology |
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UCS1002-3 Datasheet(HTML) 82 Page - Microchip Technology |
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82 / 114 page  UCS1002-3 DS20006852A-page 82 2023 Microchip Technology Inc. and its subsidiaries 10.13 Custom Emulation Configuration Registers The Custom Emulation Configuration registers store the values used by the Custom Charger Emulation circuitry. The Custom Charger Emulation profile is set up as three stimuli and the respective responses. The contents of registers 40h to 4Ch are retained in Sleep. bit 3-0 S3_TH[3:0]: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, STIM3[2:0] = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. Name Bits Address Cof Default Custom Emulation Config 8 40h R/W 01h Custom Emulation Stimulus 1 – Config 1 8 41h R/W 00h Custom Emulation Stimulus 1 – Config 2 8 42h R/W 00h Custom Emulation Stimulus 1 – Config 3 8 43h R/W 00h Custom Emulation Stimulus 1 – Config 4 8 44h R/W 00h Custom Emulation Stimulus 2 – Config 1 8 45h R/W 00h Custom Emulation Stimulus 2 – Config 2 8 46h R/W 00h Custom Emulation Stimulus 2 – Config 3 8 47h R/W 00h Custom Emulation Stimulus 2 – Config 4 8 48h R/W 00h Custom Emulation Stimulus 3 – Config 1 8 49h R/W 00h Custom Emulation Stimulus 3 – Config 2 8 4Ah R/W 00h Custom Emulation Stimulus 3 – Config 3 8 4Bh R/W 00h Custom Emulation Stimulus 3 – Config 3 8 4Ch R/W 00h REGISTER 10-34: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 3Bh)(Note 1) (CONTINUED) |
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