UCS1002-3 datasheet(28/114 Pages) MICROCHIP

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UCS1002-3

DS20006852A-page 28

 2023 Microchip Technology Inc. and its subsidiaries

When using the Latch fault handler and the user has

reactivated the device by clearing the ERR bit (see

Section 10.3 “Status Registers”), or toggling the

PWR_EN control, the UCS1002-3 checks that all of the

error conditions are removed. If using Auto-Recovery

Fault Handler, after the tCYCLE time period, the

UCS1002-3 checks that all of the error conditions are

removed.

If all of the error conditions are removed, the UCS1002-

3 returns to the Active state or Detect state as

applicable. Returning to the Active state causes the

UCS1002-3 to restart the selected mode (see

Section 9.2 “Active Mode Selection”).

If the device is in the Error state and a Removal

Detection event occurs, it checks the error conditions

and then returns to the power state as defined by the

PWR_EN, M1, M2, EM_EN, and S0 controls.

5.2

Supply Voltages

5.2.1

VDD SUPPLY VOLTAGE

The UCS1002-3 requires 4.5V to 5.5V to be present on

the VDD pin for core device functionality. Core device

functionality consists of maintaining register states,

wake-up upon SMBus/I2C query and Attach Detection.

5.2.2

VS SOURCE VOLTAGE

VS can be a separate supply and can be greater than

VDD to accommodate high-current applications in

which current path resistances result in unacceptable

voltage drops that may prevent optimal charging of

some portable devices.

5.2.3

BACK-VOLTAGE DETECTION

Whenever the following conditions are true, the port

power switch, the VBUS bypass switch, and the high-

speed data switch are disabled, and a back-voltage

event is flagged. This causes the UCS1002-3 to enter

the Error power state (see Section 5.1.5 “Error State

Operation”).

• The VBUS voltage exceeds the VS voltage by

VBV_TH and the port power switch is closed. The

port power switch is immediately opened. If the

condition lasts for longer than tMASK, then the

UCS1002-3 enters the Error state. Otherwise, the

port power switch is turned ON as soon as the

condition is removed.

• The VBUS voltage exceeds the VDD voltage by

VBV_TH and the VBUS bypass switch is closed.

The bypass switch is immediately opened. If the

condition lasts for longer than tMASK, then the

UCS1002-3 enters the Error state. Otherwise, the

bypass switch is turned ON as soon as the

condition is removed.

5.2.4

BACK-DRIVE CURRENT

PROTECTION

If a self-powered portable device is attached, it may

drive the VBUS port to its power supply voltage level;

however, the UCS1002-3 is designed such that leak-

age current from the VBUS pins to the VDD or VS pins

shall not exceed IBD_1 (if the VDD voltage is zero) or

IBD_2 (if the VDD voltage exceeds VDD_TH).

5.2.5

UNDERVOLTAGE LOCKOUT ON VS

The

UCS1002-3

requires

minimum

voltage

(VS_UVLO) to be present on the VS pin for Active power

state.

5.2.6

OVERVOLTAGE DETECTION AND

LOCKOUT ON VS

The UCS1002-3 port power switch is disabled if the

voltage on the VS pin exceeds a voltage (VS_OV) for

longer than the specified time (tMASK). This causes the

device to enter the Error state.

5.3

Discrete Input Pins

5.3.1

COMM_SEL/ILIM INPUT

The COMM_SEL/ILIM input determines the initial ILIM

settings and the communications mode as shown in

Table 11-1.

5.3.2

SEL INPUT

The SEL pin selects the polarity of the PWR_EN

control. In addition, if the UCS1002-3 is not configured

to operate in Stand-Alone mode, the SEL pin

determines the SMBus address. See Table 11-2. The

SEL pin state is latched upon device power-up and

further changes have no effect.

5.3.3

M1, M2, AND EM_EN INPUTS

The M1, M2, and EM_EN input controls determine the

Active mode and affect the power state (see Table 5-2

and Table 9-1). When these controls are all set to ‘0’

and PWR_EN is enabled, the UCS1002-3 Attach and

Removal Detection feature is disabled. In SMBus

mode, the M1, M2, and EM_EN pin states are ignored

by the UCS1002-3 if the PIN_IGNORE configuration bit

is set (see Section 10.4.3 “Switch Configuration

EM_EN_SET configuration bits (see Section 10.4.3

“Switch Configuration Register”) are checked along

with the pins.

Note:

If it is necessary to connect any of the

control pins except the COMM_SEL/ILIM

or SEL pins via a resistor to VDD or GND,

the resistor value must not exceed 100 k



in order to meet the VIH and VIL

specifications.

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