UCS1002-3 datasheet(56/114 Pages) MICROCHIP

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UCS1002-3

DS20006852A-page 56

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10.4

Configuration Registers

The Configuration registers control basic device

functionality.

10.4.1

GENERAL CONFIGURATION

The contents of this register are retained in Sleep.

bit 1-0

PWR_STATE[1:0]: Indicates the current power state. These bits are set and automatically cleared as the

power state changes. (Note 1)

00 = Sleep

01 = Detect

10 = Active

11 = Error

Note 1: Accessing the SMBus/I2C causes the UCS1002-3 to leave the Sleep state. As a result, the

PWR_STATE[1:0] bits are never read as 00b.

PIN STATUS REGISTER (ADDRESS 14h) (CONTINUED)

Name

Bits

Address

Cof.

Default

General Configuration

15h

R/W

01h

Emulation Configuration

16h

R/W

8Ch

Switch Configuration

17h

R/W

04h

Attach Detect Configuration

18h

R/W

47h

High-Speed Switch Configuration

25h

R/W

14h

GENERAL CONFIGURATION REGISTER (ADDRESS 15h)

R/W-0

U-x

R/W-0

R/W-1

ALERT_MASK

—

ALERT_LINK DISCHARGE

RATION_EN

RATION_RST

RATION_BEH[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ALERT_MASK: Disables the ALERT# pin from asserting in the case of an error.

1 = The ALERT# pin is not asserted in the event of an error condition.

0 = The ALERT# pin is asserted if an error condition or an indicator event is detected.

bit 6

Unimplemented

bit 5

ALERT_LINK: Links the ALERT# pin to be asserted when the LOW_CUR and/or TREG bits are set.

1 = The ALERT# pin is asserted if the LOW_CUR or TREG indicator bit is set.

0 = The ALERT# pin is not asserted if the LOW_CUR or TREG indicator bit is set.

bit 4

DISCHARGE: Forces the VBUS to reset and discharge when the UCS1002-3 is in the Active state.

Writing this bit to a logic ‘1’ causes the port power switch to be opened and the discharge circuitry to

activate discharging VBUS. The port power switch remains open while this bit is ‘1’. This bit is not self-

clearing.

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