R2023K datasheet(14/50 Pages) RICOH

14 / 50 page

R2023K/T

*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or

60sec. as follows:

Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of

±3.784 ms. For

example, 1-Hz clock pulses will have a duty cycle of 50

±0.3784%.

Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of

±3.784 ms.

• Control Register 2 (Address Fh)

VDSL

VDET

XST

PON

CLEN1

CTFG

WAFG

DAFG

(For Writing)

VDSL

VDET

XST

PON

CLEN1

CTFG

WAFG

DAFG

(For Reading)

Indefinite

Default Settings *)

Default settings:

Default value means read / written values when the PON bit is set to “1” due to VDD

power-on from 0 volts.

(1) VDSL

VDD Supply Voltage Monitoring Threshold Selection Bit

VDSL

Description

Selecting the VDD supply voltage monitoring threshold setting of

1.6v.

(Default)

Selecting the VDD supply voltage monitoring threshold setting of

1.3v.

The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.

(2) VDET

Supply Voltage Monitoring Result Indication Bit

VDET

Description

Indicating supply voltage above the supply voltage monitoring

threshold settings.

(Default)

Indicating supply voltage below the supply voltage monitoring

threshold settings.

Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will

hold

the setting of 1.

The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring

circuit.

Conversely, setting the VDET bit to 1 causes no event.

(3) XST

Oscillation Halt Sensing Monitor Bit

XST

Description

Sensing a halt of oscillation

Sensing a normal condition of oscillation

The XST accepts the reading and writing of 0 and 1.

The XST bit will be set to 0 when the oscillation

halt

sensing.

The XST bit will hold 0 even after the restart of oscillation.

(4) PON

Power-on-reset Flag Bit

PON

Description

Normal condition

Detecting VDD power-on -reset

(Default)

The PON bit is for sensing power-on reset condition.

* The PON bit will be set to 1 when VDD power-on from 0 volts.

The PON bit will hold the setting of 1 even

after power-on.

* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control

As a result, INTR pin stops outputting.

* The PON bit accepts only the writing of 0.

Conversely, setting the PON bit to 1 causes no event.

R2023K Datasheet(PDF) 14 Page - RICOH electronics devices division

R2023K Datasheet(HTML) 14 Page - RICOH electronics devices division

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL