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R2023K Datasheet(PDF) 36 Page - RICOH electronics devices division |
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R2023K Datasheet(HTML) 36 Page - RICOH electronics devices division |
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36 / 50 page ![]() R2023K/T 36 Power-on Reset, Oscillation Halt Sensing, and Supply Voltage Monitoring • PON, XST, and VDET The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 1.6 or 1.3V. Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and XST bit is for the oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are activated to “H”. However, XST bit is activated to “L”. The PON and VDET accept only the writing of 0, but XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is set to 0, and XST is indefinite. The functions of these three monitor bits are shown in the table below. PON XST VDET Function Monitoring for the power-on reset function Monitoring for the oscillation halt sensing function a drop in supply voltage below a threshold voltage of 1.6 or 1.3V Address D4 in Address Fh D5 in Address Fh D6 in Address Fh Activated High Low High When VDD power up from 0v 1 Indefinite 0 accept the writing 0 only Both 0 and 1 0 only The relationship between the PON, XST , and VDET is shown in the table below. PON XST VDET Conditions of supply voltage and oscillation Condition of oscillator, and back-up status 0 0 0 Halt on oscillation, but no drop in VDD supply voltage below threshold voltage Halt on oscillation cause of condensation etc. 0 0 1 Halt on oscillation and drop in VDD supply voltage below threshold voltage, but no drop to 0V Halt on oscillation cause of drop in back-up battery voltage 0 1 0 No drop in VDD supply voltage below threshold voltage and no halt in oscillation Normal condition 0 1 1 Drop in VDD supply voltage below threshold voltage and no halt on oscillation No halt on oscillation, but drop in back-up battery voltage 1 * * Drop in supply voltage to 0v Power-up from 0v, |
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