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R2023K Datasheet(PDF) 23 Page - RICOH electronics devices division

Part # R2023K
Description  2-wire Serial Interface Real Time Clock IC
PDF  50 Pages
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

R2023K Datasheet(HTML) 23 Page - RICOH electronics devices division

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R2023K/T
23
• Transmission System of I2C-Bus
(1) Start Condition and Stop Condition
In I
2C-Bus, SDA must be kept at a certain state while SCL is at the “H” state during data transmission as shown
below.
SCL
SDA
tSU;DAT
tHD;DAT
The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L”
when the SCL and the SDA are “H” activates the Start Condition and access is started. Changing the SDA from “L”
to “H” when the SCL is “H” activates Stop Condition and accessing stopped. Generation of Start and Stop
Conditions are always made by the master (see the figure below).
SCL
SDA
tHD;STA
tSU;STO
Start Condition
Stop Condition
(2) Data transmission and its acknowledge
After Start condition is entered, data is transmitted by 1byte (8bits).
Any bytes of data may be serially transmitted.
The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted.
The acknowledge signal is sent immediately after falling to “L” of SCL 8bit clock pulses of data is transmitted, by
releasing the SDA by the transmission side that has asserted the bus at that time and by turning SDA to “L” by
receiving side.
When transmission of 1byte data next to preceding 1byte of data is received the receiving side
releases the SDA pin at falling edge of the SCL 9bit of clock pulses or when the receiving side switches to the
transmission side it starts data transmission.
When the master is receiving side, it generates no acknowledge
signal after last 1byte of data from the slave to tell the transmitter that data transmission has completed.
The
slave side (transmission side) continues to release the SDA pin so that the master will be able to generate Stop
Condition, after falling edge of the SCL 9bit of clock pulses.
SCL
from the master
SDA from
the transmission side
SDA from
the receiving side
12
89
Acknowledge
signal
Start
Condition



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