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PIC18F6X2X Datasheet(PDF) 104 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 386 page ![]() PIC18F6X2X/8X2X DS39612A-page 102 Advance Information 2003 Microchip Technology Inc. REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2-0 CCPxIP: CCPx Interrupt Priority bit (ECCP3, CCP4 and CCP5) 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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