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XCVU29P Datasheet(PDF) 28 Page - Advanced Micro Devices

Part # XCVU29P
Description  Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics
PDF  68 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

XCVU29P Datasheet(HTML) 28 Page - Advanced Micro Devices

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Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most
accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using
this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 27.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation
delay of the PCB trace.
Table 27: Output Delay Measurement Methodology
Description
I/O Standard Attribute
RREF
(Ω)
CREF1 (pF) VMEAS
(V)
VREF (V)
LVCMOS, 1.2V
LVCMOS12
1M
0
0.6
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVDCI, HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
50
0
VREF
0.75
LVDCI, HSLVDCI, 1.8V
LVDCI_15, HSLVDCI_18
50
0
VREF
0.9
HSTL (high-speed transceiver logic), class I, 1.2V
HSTL_I_12
50
0
VREF
0.6
HSTL, class I, 1.5V
HSTL_I
50
0
VREF
0.75
HSTL, class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSUL (high-speed unterminated logic), 1.2V
HSUL_12
50
0
VREF
0.6
SSTL12 (stub series terminated logic), 1.2V
SSTL12
50
0
VREF
0.6
SSTL135, 1.35V
SSTL135
50
0
VREF
0.675
SSTL15, 1.5V
SSTL15
50
0
VREF
0.75
SSTL18, class I, 1.8V
SSTL18_I
50
0
VREF
0.9
POD10, 1.0V
POD10
50
0
VREF
1.0
POD12, 1.2V
POD12
50
0
VREF
1.2
DIFF_HSTL, class I, 1.2V
DIFF_HSTL_I_12
50
0
VREF
0.6
DIFF_HSTL, class I, 1.5V
DIFF_HSTL_I
50
0
VREF
0.75
DIFF_HSTL, class I, 1.8V
DIFF_HSTL_I_18
50
0
VREF
0.9
DIFF_HSUL, 1.2V
DIFF_HSUL_12
50
0
VREF
0.6
DIFF_SSTL12, 1.2V
DIFF_SSTL12
50
0
VREF
0.6
DIFF_SSTL135, 1.35V
DIFF_SSTL135
50
0
VREF
0.675
DIFF_SSTL15, 1.5V
DIFF_SSTL15
50
0
VREF
0.75
DIFF_SSTL18, 1.8V
DIFF_SSTL18_I
50
0
VREF
0.9
DIFF_POD10, 1.0V
DIFF_POD10
50
0
VREF
1.0
DIFF_POD12, 1.2V
DIFF_POD12
50
0
VREF
1.2
LVDS (low-voltage differential signaling), 1.8V
LVDS
100
0
02
0
SUB_LVDS, 1.8V
SUB_LVDS
100
0
02
0
MIPI D-PHY (high speed) 1.2V
MIPI_DPHY_DCI_HS
100
0
02
0
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DS923 (v1.10) April 26, 2019
www.xilinx.com
Product Specification
28
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