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XCVU29P Datasheet(PDF) 59 Page - Advanced Micro Devices

Part # XCVU29P
Description  Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics
PDF  68 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

XCVU29P Datasheet(HTML) 59 Page - Advanced Micro Devices

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High Bandwidth Memory Controller
The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs with
integrated high-bandwidth memory (HBM).
Table 73: Maximum Performance for High Bandwidth Memory Controller
Symbol
Description
Speed Grade and VCCINT Operating Voltages
Units
0.90V
0.85V
0.72V
-3
-2
-1
-2
FHBM_REF_CLK
HBM controller reference clock maximum frequency
450.00
450.00
450.00
450.00
MHz
FACLK
AXI interface clock maximum frequency
450.00
450.00
400.00
400.00
MHz
FAPB
Advance peripheral bus (APB) clock maximum
frequency
100.00
100.00
100.00
100.00
MHz
FHBM
HBM maximum line rate interface to DRAM
1800
1800
1600
1800
Mb/s
System Monitor Specifications
Table 74: System Monitor Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C
ADC Accuracy1
Resolution
10
–
–
Bits
Integral nonlinearity2
INL
–
–
±1.5
LSBs
Differential nonlinearity
DNL
No missing codes, guaranteed monotonic
–
–
±1
LSBs
Offset error
Offset calibration enabled
–
–
±2
LSBs
Gain error
–
–
±0.4
%
Sample rate
–
–
0.2
MS/s
RMS code noise
External 1.25V reference
–
–
1
LSBs
On-chip reference
–
1
–
LSBs
ADC Accuracy at Extended Temperatures
Resolution
Tj = –55°C to 125°C
10
–
–
Bits
Integral nonlinearity2
INL
Tj = –55°C to 125°C
–
–
±1.5
LSBs
Differential nonlinearity
DNL
No missing codes, guaranteed monotonic
Tj = –55°C to 125°C
–
–
±1
Analog Inputs2
ADC input ranges
Unipolar operation
0
–
1
V
Bipolar operation
–0.5
–
+0.5
V
Unipolar common mode range (FS input)
0
–
+0.5
V
Bipolar common mode range (FS input)
+0.5
–
+0.6
V
Maximum external channel input ranges
Adjacent channels set within these ranges should
not corrupt measurements on adjacent channels
–0.1
–
VCCADC
V
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DS923 (v1.10) April 26, 2019
www.xilinx.com
Product Specification
59
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