XCVU29P datasheet(34/68 Pages) AMD

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Device Pin-to-Pin Output Parameter Guidelines

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the

device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado

Design Suite timing report for the actual pin-to-pin values.

Table 35: Global Clock Input to Output Delay Without MMCM (Near Clock Region)

Symbol

Description1

Device

Speed Grade and VCCINT Operating Voltages

Units

0.90V

0.85V

0.72V

-3

-2

-1

-2

SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM

TICKOF

Global clock input and output flip-flop without

MMCM (near clock region)

XCVU3P

4.41

4.77

5.09

5.48

XCVU5P

4.41

4.77

5.09

5.48

XCVU7P

4.41

4.77

5.09

5.48

XCVU9P

4.41

4.77

5.09

5.48

XCVU11P

4.22

4.59

4.90

5.27

XCVU13P

4.22

4.59

4.90

5.27

XCVU27P

4.22

4.59

4.90

5.27

XCVU29P

4.22

4.59

4.90

5.27

XCVU31P

4.22

4.59

4.90

5.27

XCVU33P

4.22

4.59

4.90

5.27

XCVU35P

4.22

4.59

4.90

5.27

XCVU37P

4.22

4.59

4.90

5.27

XQVU3P

N/A

4.77

5.09

5.48

XQVU7P

N/A

4.77

5.09

5.48

XQVU11P

N/A

4.59

4.90

5.27

Notes:

This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics

DS923 (v1.10) April 26, 2019

www.xilinx.com

Product Specification

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