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XCVU29P Datasheet(PDF) 32 Page - Advanced Micro Devices |
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XCVU29P Datasheet(HTML) 32 Page - Advanced Micro Devices |
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32 / 68 page  MMCM Switching Characteristics Table 33: MMCM Specification Symbol Description Speed Grade and VCCINT Operating Voltages Units 0.90V 0.85V 0.72V -3 -2 -1 -2 MMCM_FINMAX Maximum input clock frequency 1066 933 800 933 MHz MMCM_FINMIN Minimum input clock frequency 10 10 10 10 MHz MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max MMCM_FINDUTY Input duty cycle range: 10–49 MHz 25–75 % Input duty cycle range: 50–199 MHz 30–70 % Input duty cycle range: 200–399 MHz 35–65 % Input duty cycle range: 400–499 MHz 40–60 % Input duty cycle range: >500 MHz 45–55 % MMCM_FMIN_PSCLK Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum dynamic phase shift clock frequency 550 500 450 500 MHz MMCM_FVCOMIN Minimum MMCM VCO frequency 800 800 800 800 MHz MMCM_FVCOMAX Maximum MMCM VCO frequency 1600 1600 1600 1600 MHz MMCM_FBANDWIDTH Low MMCM bandwidth at typical1 1.00 1.00 1.00 1.00 MHz High MMCM bandwidth at typical1 4.00 4.00 4.00 4.00 MHz MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs2 0.12 0.12 0.12 0.12 ns MMCM_TOUTJITTER MMCM output jitter Note 3 MMCM_TOUTDUTY MMCM output clock duty cycle precision4 0.165 0.20 0.20 0.20 ns MMCM_TLOCKMAX MMCM maximum lock time for MMCM_FPFDMIN 100 100 100 100 µs MMCM_FOUTMAX MMCM maximum output frequency 891 775 667 725 MHz MMCM_FOUTMIN MMCM minimum output frequency4, 5 6.25 6.25 6.25 6.25 MHz MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum frequency at the phase frequency detector 550 500 450 500 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector 10 10 10 10 MHz MMCM_TFBDELAY Maximum delay in the feedback path 5 ns Max or one clock cycle MMCM_FDPRCLK_MAX Maximum DRP clock frequency 250 250 250 250 MHz Notes: 1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. 4. Includes global clock buffer. 5. Calculated as FVCO/128 assuming output duty cycle is 50%. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 32 Send Feedback |
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