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L99PM60J Datasheet(PDF) 51 Page - STMicroelectronics |
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L99PM60J Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 75 page ![]() L99PM60J ST SPI Doc ID 18309 Rev 6 51/75 7.1.6 Address mapping The RAM memory area consists of 8 bit registers. For the device information (ROM memory area) the eight bits of the memory cell are used. All unused RAM and ROM addresses are read as ‘0’. Note: 1 The register definition for RAM address 00H is unused. A register value of all 0 must cause the device to enter a failsafe state (interpreted as ‘SDI stuck to GND’ failure). 2 ROM address 3FH is unused. An attempt to access this address must be recognized as a communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a failsafe state. 7.1.7 Write operation The write operation starts with a Command Byte followed by 1 data byte. Table 39. Addressing mapping RAM Address Description Access ROM Address Description Access 3FH <Configuration> R/W 3FH Reserved N/A 14H Status register 4 R 3EH <SPI frame ID> Includes frame width and availability of watchdog R 13H Status register 3 R 12H Status register 2 R … Unused N/A 11H Status register 1 R 03H <product code 2> Unique product identifier N/A 02H Control register 2 R/W 01H Control register 1 R/W 02H <product code 1> Unique product identifier R 00H Reserved R/W 01H <silicon version> Indicates Design Version R 00H <ID Header> Device family, max address of device information R Table 40. Write command format MSB LSB Command byte Op Code Address 0 0 A5 A4 A3 A2 A1 A0 Data byte D7 D6 D5 D4 D3 D2 D1 D0 |
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