L99PM60J datasheet(22/75 Pages) STMICROELECTRONICS

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Detailed description

L99PM60J

22/75

Doc ID 18309 Rev 6

2.8

Reset output (NRESET)

If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output

“NRESET” is pulled up by internal pull up resistor to V1 voltage after a reset delay time

tReset. This is necessary for a defined start of the micro controller when the application is

switched on. Since the NRESET output is realized as an open drain output it is also possible

to connect an external NRESET open drain NRESET source to the output. It must be

considered that as soon the NRESET is released from the L99PM60J the watchdog timing

starts.

A reset pulse tReset is generated in case of:

●

V1 drops below Vrth (configurable by SPI) for more than V1UFT

●

Watchdog failure

2.9

LIN bus interface

General features:

●

Speed communication up to 20kbit/s.

●

LIN 2.1 compliant (SAE J2602 compatible) transceiver.

●

Function range from +40V to -18V DC at LIN Pin.

●

GND disconnection fail safe at module level.

●

Off mode: does not disturb network.

●

GND shift operation at system level.

●

Micro controller Interface with CMOS compatible I/O pins.

●

ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

●

Matched output slopes and propagation delay

In order to further reduce the current consumption in standby mode, the integrated LIN bus

interface offers an ultra low current consumption.

2.9.1

Error handling

The L99PM60J provides the following 3 error handling features which are not described in

the LIN Spec. Revision 2.1, but are realized in different stand alone LIN transceivers / micro

controllers to switch the application back to normal operation mode.

At Vs > Vpor (i.e. Vs power-on reset threshold), the LIN transceiver is enabled.

The LIN transmitter is disabled in case of the following errors:

●

Dominant TxDL time out

●

LIN permanent recessive

●

Thermal shutdown 1

●

VS overvoltage / VS undervoltage

The LIN receiver is not disabled in case of any failure condition.

Dominant TxD time out

If TXD is in dominant state (low) for more than tdom(TXDL)(typ) the transmitter is disabled. The

status bit is latched and can be read and optionally cleared by SPI. The transmitter remains

disabled until the status register is cleared. This feature can be disabled via SPI.

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