L99PM60J datasheet(16/75 Pages) STMICROELECTRONICS

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Detailed description

L99PM60J

16/75

Doc ID 18309 Rev 6

watchdog via the SPI. The trigger is finally accepted when the CSN input becomes HIGH

after the transmission of the SPI word.

Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window

watchdog Subsequently, the micro controller has to serve the watchdog by alternating the

watchdog trigger bit within the safe trigger area (refer to watchdog chapter). A correct

watchdog trigger signal immediately starts the next cycle.

After 8 watchdog failures in sequence, the V1 regulator is switched off for tV1Off If

subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off

and the device goes into VBAT-standby mode until a walk-up occurs.

In case of a Watchdog failure, the outputs (RELx, OUTx) are switched off and the device

enters fail safe mode (i. e. all control registers are set to default values, except OUT1

when not used as FSO.)

The following diagrams illustrate the Watchdog behavior of the L99PM60J. The diagrams

are split into 3 parts. First diagram shows the functional behavior of the watchdog without

any error. The second diagram covers the behavior covering all the error conditions, which

can affect the watchdog behavior. Third diagram shows the transition in and out of FLASH

mode. All three diagrams can be overlapped to get all the possible state transitions under all

circumstances. For a better readability, those transitions have been split in normal

operating, operating with errors and flash mode.

Figure 5.

Watchdog in normal operating mode (no errors)

L99PM60J Datasheet(PDF) 16 Page - STMicroelectronics