MFRC522 datasheet(74/109 Pages) NXP

74 / 109 page

112132

Product data sheet

Rev. 3.2 — 22 May 2007

74 of 109

NXP Semiconductors

MFRC522

Contactless Reader IC

18.3.1.7

Receive Command

The MFRC522activates the receiver path and waits for any data stream to be received.

The correct settings have to be chosen before starting this command.

This command terminates automatically when the received data stream ends. This is

indicated either by the end of frame pattern or by the length byte depending on the

selected framing and speed.

Remark: If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive

command does not terminate automatically. It has to be terminated by

activating any other command in the CommandReg register.

18.3.1.8

Transceive Command

This circular command repeats transmitting data from the FIFO and receiving data from

the RF field continuously. The first action is transmitting and after a transmission the

command is changed to receive a data stream.

Each transmission process has to be started by setting bit StartSend in the register

BitFramingReg to logic 1. This command has to be cleared by software by writing any

command to register CommandReg e.g. the command idle.

Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will

never leave the receiving state, because the receiving will not be cancelled

automatically.

18.3.1.9

MFAuthent Command

This command handles the MIFARE® authentication to enable a secure communication to

any MIFARE® classic card. The following data shall be written to the FIFO before the

command can be activated:

• Authentication command code (60h, 61h)

• Block address

• Sector key byte 0

• Sector key byte 1

• Sector key byte 2

• Sector key byte 3

• Sector key byte 4

• Sector key byte 5

• Card serial number byte 0

• Card serial number byte 1

• Card serial number byte 2

• Card serial number byte 3

In total 12 bytes shall be written to the FIFO.

Remark: When the MFAuthent command is active, any FIFO access is blocked. Anyhow

if there is an access to the FIFO, the bit WrErr in the ErrorReg register is set.

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