RIVA128ZX datasheet(63/85 Pages) STMICROELECTRONICS

63 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

63/85

IN-CIRCUIT BOARD TESTING

The RIVA128ZX has a number of features designed to support in-circuit board testing. These include:

• Dedicated test mode input and dual-function test mode select pins selecting the following modes:

- Pin float

- Parametric NAND tree

- All outputs driven high

- All outputs driven low

• Checksum test

• Test registers

12.1 TEST MODES

Primary test control is provided by the dedicated TESTMODE input pin. The RIVA128ZX is in normal op-

erating mode when this pin is deasserted. When TESTMODE is asserted, MP_AD[3:0] are reassigned as

TESTCTL[3:0] respectively. Test modes are selected asynchronously through a combination of the pin

states shown in Table 21.

Table 21.

Test mode selection and descriptions

12.2 CHECKSUM TEST

The RIVA128ZX hardware checksum feature sup-

ports testing of the entire pixel datapath at full video

rates from the framebufferthrough to the DAC inputs.

Each of the three RGB colors can be tested to pro-

vide a correlation between the intended and actual

display. Checksums are accumulated during active

(unblanked) display. Note that the checksum mech-

anism does not check the DAC outputs (i.e. what is

physically being displayed on the monitor).

For a given image (which can be a real application’s

image or a specially prepared test card), theoretical-

ly derived checksum values can be calculated for a

selected RGB color, which are then compared with

the RIVA128ZX hardware checksum value. Alterna-

tively the checksum value from a known good chip

can be used as the reference.

Hardware checksum accumulation is not affected by

the horizontal and vertical synchronization wave-

forms or timings. Any discrepancy between the cal-

culated and RIVA128ZX hardware accumulated

checksum values therefore indicates a problem in

the device or system being tested. Details of pro-

gramming the RIVA128ZX checksum are given in

the RIVA128ZX

Programming Reference Manual

[2].

Test mode

TESTCTL[3:0]

Description

321

Parametric

NAND tree

A single parametric NAND tree is provided to give a quiescent environ-

ment in which to test VIL and VIH without requiring core activity.

This capability is provided in the pads by chaining all I and I/O paths to-

gether via two input NAND gates. The chain begins with one input of the

first NAND gate tied to VDD while the other input is connected to the first

device pin on the NAND tree. The output of this gate then becomes the in-

put of the next NAND gate in the tree and so on until all pad input paths

have been connected. The final NAND gate output is connected to an out-

put-only pin whose normal functionality is disabled in NAND tree mode.

The NAND tree length is therefore equal to the number of I and I/O pins in

the RIVA128ZX. Output -only pins are not connected into the NAND tree.

Pin float

All pin output drivers are tristated in this test mode so that pin leakage

current (IIL,IIH,IOZL,IOZH) can be measured.

Outputs high

All pin output drivers drive a high output state in this test mode so that

output high voltage (VOH at IOH) can be measured.

Outputs low

All pin output drivers drive a low output state in this test mode so that out-

put low voltage (VOL at IOL) can be measured.

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