RIVA128ZX datasheet(15/85 Pages) STMICROELECTRONICS

15 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

15/85

the AGP bridge chip and RIVA128ZX are the only

devices on the AGP bus - all other I/O devices re-

main on the PCI bus.

The add-in slot defined for AGP uses a new con-

nector body (for electrical signaling reasons)

which is not compatible with the PCI connector;

PCI and AGP boards are not mechanically inter-

changeable.

AGP accesses differ from PCI in that they are

pipelined. This compares with serialized PCI

transactions, where the address, wait and data

phases need to complete before the next transac-

tion starts. AGP transactions can only access sys-

tem memory - not other PCI devices or CPU. Bus

mastering accesses can be either PCI or AGP-

style.

Full details of AGP are given in the

Accelerated

Graphics Port Interface Specification [3] published

by Intel Corporation.

4.1

RIVA128ZX AGP INTERFACE

The RIVA128ZX glueless interface to AGP 1.0 is shown in Figure 2.

Figure 2.

AGP interface pin connections

4.2

AGP BUS TRANSACTIONS

AGP bus commands supported

The following AGP bus commands are supported

by the RIVA128ZX:

- Read

- Read (hi-priority)

PCI transactions on the AGP bus

PCI transactions can be interleaved with AGP

transactions including between pipelined AGP

data transfers. A basic PCI transaction on the AGP

interface is shown in Figure 3. If the PCI target is

a non AGP compliant master, it will not see

AGPST[2:0] and the transaction appears to be on

a PCI bus. For AGP aware bus masters,

AGPST[2:0] indicate that permission to use the in-

terface has been granted to initiate a request and

not to move AGP data.

PCICBE[3:0]#

PCIAD[31:0]

AGPPIPE#

PCIDEVSEL#

PCIIRDY#

PCITRDY#

PCISTOP#

PCIIDSEL

PCIREQ#

PCIGNT#

PCICLK

PCIRST#

PCIPAR

PCIINTA#

RIVA128ZX

AGPST[2:0]#

AGPRBF#

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