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RIVA128ZX Datasheet(PDF) 51 Page - STMicroelectronics

Part # RIVA128ZX
Description  128-BIT 3D MULTIMEDIA ACCELERATOR
PDF  85 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

RIVA128ZX Datasheet(HTML) 51 Page - STMicroelectronics

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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
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8.4
656 MASTER MODE
Table 15 shows the Video Port pin definition when
the RIVA128ZX is configured in ITU-R-656 Master
Mode. Before entering this mode, RIVA128ZX dis-
ables all Video Port devices so that the bus is tri-
stated. The RIVA128ZX will then enable the video
656 master device through the serial bus. In this
mode, the video device outputs the video data
continuously at the PIXCLK rate.
Table 15.
656 master mode pin definition
The 656 Master Mode assumes that VID[7:0] and
PIXCLK can be tri-stated when the slave is inac-
tive. If a slave cannot tri-state all its signals, an ex-
ternal tri-state buffer is needed.
Video data capture
Video Port pixel data is clocked into the port by the
external pixel clock and then passed to the
RIVA128ZX’s video capture FIFO.
Pixel data capture is controlled by the ITU-R-656
codes embedded in the data stream; each active
line beginning with SAV (start active video) and
ending with EAV (end active video).
In normal operation, when SAV = x00, capture of
video data begins, and when EAV = xx1, capture
of video data ends for that line. When VBI (Vertical
Blanking Interval) capture is active, these rules are
modified.
656 master mode timing specification
Figure 62.
656 Master Mode timing diagram
Table 16.
ITU-R-656 Master Mode timing parameters
NOTE
1
VACTIVE indicates that valid pixel data is being transmitted across the video port.
Table 17.
YUV (YCbCr) byte ordering
Normal Mode
656 Master Mode
MPCLK
PIXCLK
MPAD[7:0]
VID[7:0]
MPFRAME#
Not used
MPDTACK#
Not used
MPSTOP#
Not used
Symbol
Parameter
Min.
Max.
Unit
Notes
t3
VID[7:0] hold from PIXCLK high
0
ns
t4
VID[7:0] setup to PIXCLK high
5
ns
t5
PIXCLK cycle time
35
ns
1st byte
2nd byte
3rd byte
4th byte
5th (next
dword)
6th byte
7th byte
U[7:0]
Y0[7:0]
V[7:0]
Y1[7:0]
U[7:0]
Y0[7:0]
V[7:0]
Cb[7:0]
Y0[7:0]
Cr[7:0]
Y1[7:0]
Cb[7:0]
Y0[7:0]
Cr[7:0]
t5
t4
t3
t4
t3
t4
t3
PIXCLK
VID[7:0]



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