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RIVA128ZX Datasheet(PDF) 84 Page - STMicroelectronics |
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RIVA128ZX Datasheet(HTML) 84 Page - STMicroelectronics |
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84 / 85 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 84/85 Byte offsets 0x67 - 0x64 Power Management Control/Status Register (0x67 - 0x64) Byte offset 0xFF - 0x50 0x67 0x66 0x65 0x64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76543 210 Bits Function RW I 31:2 Reserved R- 0 1:0 POWER_STATE indicates and controls the current power state of RIVA128ZX. Two power states are supported D0 (full power) and D3hot (low power). 0x0 = D0 0x3 = D3hot The RIVA128ZX does not physically change its power consumption when POWER_STATE is modified. The device can be transitioned from D3 to D0 either by writing to this register or by applying a hard reset to the PCIRST# pin. RW 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 76543 210 Reserved = 0x00000000 |
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