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RIVA128ZX Datasheet(PDF) 53 Page - STMicroelectronics |
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RIVA128ZX Datasheet(HTML) 53 Page - STMicroelectronics |
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53 / 85 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA128ZX 53/85 9 BOOT ROM INTERFACE BIOS and initialization code for the RIVA128ZX is accessed from a 32KByte ROM. The RIVA128ZX mem- ory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes of data respectively. The unique decode to the ROM device is provided by the ROMCS# chip select signal. Figure 63. ROM interface ROM interface timing specification Figure 64. ROM interface timing diagram FBD[15:0] FBD[31:24] ROMCS# D[7:0] A[15:0] CS ROM WE RIVA128ZX FBD[17] OE FBD[16] ROM Read tBAS tBRCS tBAH tBRCA tBRV tBRH tBDBZ tBDS tBDH tBDZ tBOS address data FDB[15:0] ROMCS# OE# (FBD[16]) WE# (FBD[17]) FDB[31:24] ROM Write tBAS tBRCS tBAH tBWDS tBWDH address data FDB[15:0] ROMCS# OE# (FBD[16]) WE# (FBD[17]) FDB[31:24] tBWS tBWL tBOH |
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