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HD6417618A Datasheet(PDF) 386 Page - Renesas Technology Corp |
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HD6417618A Datasheet(HTML) 386 Page - Renesas Technology Corp |
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386 / 646 page ![]() Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 6.00 Jun. 12, 2007 Page 354 of 610 REJ09B0131-0600 Bit Bit Name Initial value R/W Description 7 6 RTRG1 RTRG0 0 0 R/W R/W Receive FIFO Data Trigger Set the specified receive trigger number. The receive data full (RDF) flag in the serial status register (SCFSR) is set when the number of receive data stored in the receive FIFO register (SCFRDR) exceeds the specified trigger number shown below. • Asynchronous mode 00: 1 01: 4 10: 8 11: 14 • Synchronous mode 00: 1 01: 2 10: 8 11: 14 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Trigger 1 and 0 Set the specified transmit trigger number. The transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR) is set when the number of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the specified trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of remaining bytes in SCFTDR when the TDFE flag is set to 1. |
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