7643 datasheet(362/424 Pages) RENESAS

362 / 424 page

7643 Group

REJ09B0133-0200

APPENDIX

3.4 Countermeasure against noise

Rev.2.00

Aug 28, 2006

page 39 of 98

(2) Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O pins as short as possible.

• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is

connected to an oscillator and the VSS pin of a microcomputer as short as possible.

• Separate the VSS pattern only for oscillation from other VSS patterns.

q Reason

If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program

failure or program runaway. Also, if a potential difference is caused by the noise between the

VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input

in the microcomputer.

Noise

XIN

XOUT

VSS

XIN

XOUT

VSS

N.G.

O.K.

3.4 Countermeasures against noise

Countermeasures against noise are described below. The following countermeasures are effective against

noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual

use.

3.4.1 Shortest wiring length

The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.

The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.

(1) Wiring for RESET pin

Make the length of wiring which is connected to the RESET pin as short as possible. Especially,

connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within

20mm).

q Reason

The width of a pulse input into the RESET pin is determined by the timing necessary conditions.

If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is

released before the internal state of the microcomputer is completely initialized. This may cause

a program runaway.

Fig. 3.4.1 Wiring for the RESET pin

RESET

Reset

circuit

Noise

VSS

Reset

circuit

VSS

RESET

VSS

N.G.

O.K.

Fig. 3.4.2 Wiring for clock I/O pins

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