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OMAP3530-HiRel Datasheet(PDF) 30 Page - Texas Instruments

Part # OMAP3530-HiRel
Description  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel Datasheet(HTML) 30 Page - Texas Instruments

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)
BALL
BALL
PIN
MODE
TYPE
BALL
BALL
RESET
POWER
HYS
BUFFER
PULLUP
IO
BOTTOM
TOP
NAME
[5]
[6]
RESET
RESET
REL.
[10]
[11]
STRENG
/DOWN
CELL
[1]
[2]
[4]
STATE
REL.
MODE
TH
TYPE
[14]
[7]
STATE
[9]
(mA)
[13]
[8]
[12]
AE16
-
cam_d0
0
I
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
-
2
IDS
gpio_99
4
I
safe_mode
7
-
AE15
-
cam_d1
0
I
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
-
2
IDS
gpio_100
4
I
safe_mode
7
-
AD17
-
-
0
IDS
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
gpio_112
4
I
safe_mode
7
-
AE18
-
-
0
IDS
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
gpio_114
4
I
safe_mode
7
-
AD16
-
-
0
IDS
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
gpio_113
4
I
safe_mode
7
-
AE17
-
-
0
IDS
L
L
7
-
Yes
4
PU100/
LVDS/
PD100
CMOS
gpio_115
4
I
safe_mode
7
-
-
G20
sdrc_a0
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
K20
sdrc_a1
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
J20
sdrc_a2
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
J21
sdrc_a3
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
U21
sdrc_a4
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
R20
sdrc_a5
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
M21
sdrc_a6
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
M20
sdrc_a7
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
N20
sdrc_a8
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
K21
sdrc_a9
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
Y16
sdrc_a10
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
N21
sdrc_a11
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
R21
sdrc_a12
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
AA15
sdrc_a13
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
Y12
sdrc_a14
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
AA18
sdrc_ba0
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
V20
sdrc_ba1
0
O
0
0
0
vdds_io
No
4
(1)
NA
LVDS/
CMOS
-
Y15
sdrc_cke0
0
O
H
1
7
vdds_io
Yes
4
(1)
PU100/
LVDS/
PD100
CMOS
safe_mode
7
-
Y13
sdrc_cke1
0
O
H
1
7
vdds_io
Yes
4
(1)
PU100/
LVDS/
PD100
CMOS
safe_mode
7
(1)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
TERMINAL DESCRIPTION
30
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