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OMAP3530-HiRel Datasheet(PDF) 69 Page - Texas Instruments |
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OMAP3530-HiRel Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 239 page  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 – JUNE 2009 Table 2-6. External Memory Interfaces – SDRC Signals Description (continued) SIGNAL DESCRIPTION TYPE(1) BALL BOTTOM BALL TOP BALL BOTTOM BALL TOP NAME (CBB Pkg.) (CBB Pkg.) (CBC Pkg.) (CBC Pkg.) sdrc_d14 SDRAM data bit 14 IO B17 B19 - B17 sdrc_d15 SDRAM data bit 15 IO D18 A19 - B18 sdrc_d16 SDRAM data bit 16 IO D11 B3 - B7 sdrc_d17 SDRAM data bit 17 IO B10 A3 - A5 sdrc_d18 SDRAM data bit 18 IO C11 B5 - B6 sdrc_d19 SDRAM data bit 19 IO D12 A5 - A6 sdrc_d20 SDRAM data bit 20 IO C12 B8 - A8 sdrc_d21 SDRAM data bit 21 IO A11 A8 – B9 sdrc_d22 SDRAM data bit 22 IO B13 B9 - A9 sdrc_d23 SDRAM data bit 23 IO D14 A9 - B10 sdrc_d24 SDRAM data bit 24 IO C18 B21 - C21 sdrc_d25 SDRAM data bit 25 IO A19 A21 - D20 sdrc_d26 SDRAM data bit 26 IO B19 D22 - B19 sdrc_d27 SDRAM data bit 27 IO B20 D23 - C20 sdrc_d28 SDRAM data bit 28 IO D20 E22 - D21 sdrc_d29 SDRAM data bit 29 IO A21 E23 - E20 sdrc_d30 SDRAM data bit 30 IO B21 G22 - E21 sdrc_d31 SDRAM data bit 31 IO C21 G23 - G21 sdrc_ba0 SDRAM bank select 0 O H9 AB21 - AA18 sdrc_ba1 SDRAM bank select 1 O H10 AC21 - V20 sdrc_a0 SDRAM address bit 0 O A4 N22 - G20 sdrc_a1 SDRAM address bit 1 O B4 N23 - K20 sdrc_a2 SDRAM address bit 2 O B3 P22 - J20 sdrc_a3 SDRAM address bit 3 O C5 P23 - J21 sdrc_a4 SDRAM address bit 4 O C4 R22 - U21 sdrc_a5 SDRAM address bit 5 O D5 R23 - R20 sdrc_a6 SDRAM address bit 6 O C3 T22 - M21 sdrc_a7 SDRAM address bit 7 O C2 T23 - M20 sdrc_a8 SDRAM address bit 8 O C1 U22 - N20 sdrc_a9 SDRAM address bit 9 O D4 U23 - K21 sdrc_a10 SDRAM address bit 10 O D3 V22 - Y16 sdrc_a11 SDRAM address bit 11 O D2 V23 - N21 sdrc_a12 SDRAM address bit 12 O D1 W22 - R21 sdrc_a13 SDRAM address bit 13 O E2 W23 - AA15 sdrc_a14 SDRAM address bit 14 O E1 Y22 - Y12 sdrc_ncs0 Chip select 0 O H11 M22 - T21 sdrc_ncs1 Chip select 1 O H12 M23 - T20 sdrc_clk Clock IO A13 A11 - A12 sdrc_nclk Clock Invert O A14 B11 - B13 sdrc_cke0 Clock Enable 0 O H16 J22 - Y15 sdrc_cke1 Clock Enable 1 O H17 J23 - Y13 sdrc_nras SDRAM Row Access O H14 L23 - V21 sdrc_ncas SDRAM column address O H13 L22 - U20 strobe sdrc_nwe SDRAM write enable O H15 K23 - Y18 sdrc_dm0 Data Mask 0 O B7 C1 - H1 sdrc_dm1 Data Mask 1 O A16 A17 - A14 Submit Documentation Feedback TERMINAL DESCRIPTION 69 |
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