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OMAP3530-HiRel Datasheet(PDF) 20 Page - Texas Instruments

Part # OMAP3530-HiRel
Description  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel Datasheet(HTML) 20 Page - Texas Instruments

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL
PIN
MODE [4]
TYPE [5]
BALL
BALL
RESET
POWER [9]
HYS
BUFFER
PULL
IO
BOTTOM [1]
TOP [2]
NAME [3]
RESET
RESET
REL.
[10]
STRENGTH
U/D
CELL [13]
STATE [6]
REL.
MODE [8]
(mA) [11]
TYPE
STATE [7]
[12]
safe_mode
7
P21
NA
mcbsp2_fsx
0
IO
L
L
7
VDDS
Yes
4
(3)
PU/ PD
LVCMOS
gpio_116
4
IO
safe_mode
7
N21
NA
mcbsp2_ clkx
0
IO
L
L
7
VDDS
Yes
4
(3)
PU/ PD
LVCMOS
gpio_117
4
IO
safe_mode
7
R21
NA
mcbsp2_dr
0
I
L
L
7
VDDS
Yes
4
(3)
PU/ PD
LVCMOS
gpio_118
4
IO
safe_mode
7
M21
NA
mcbsp2_dx
0
IO
L
L
7
VDDS
Yes
4
(3)
PU/ PD
LVCMOS
gpio_119
4
IO
safe_mode
7
N28
NA
mmc1_clk
0
O
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_120
4
IO
safe_mode
7
M27
NA
mmc1_cmd
0
IO
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_121
4
IO
safe_mode
7
N27
NA
mmc1_dat0
0
IO
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_122
4
IO
safe_mode
7
N26
NA
mmc1_dat1
0
IO
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_123
4
IO
safe_mode
7
N25
NA
mmc1_dat2
0
IO
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_124
4
IO
safe_mode
7
P28
NA
mmc1_dat3
0
IO
L
L
7
VDDS_MMC1
Yes
8
PU/ PD
(4)
LVCMOS
gpio_125
4
IO
safe_mode
7
P27
NA
mmc1_dat4
0
IO
L
L
7
VDDS_MMC1a
No
＝
8
PD
(4)
LVCMOS
gpio_126
4
IO
safe_mode
7
P26
NA
mmc1_dat5
0
IO
L
L
7
VDDS_MMC1a
No
＝
8
PD
(4)
LVCMOS
gpio_127
4
IO
safe_mode
7
R27
NA
mmc1_dat6
0
IO
L
L
7
VDDS_MMC1a
No
8
PD
(4)
LVCMOS
gpio_128
4
IO
safe_mode
7
R25
NA
mmc1_dat7
0
IO
L
L
7
VDDS_MMC1a
No
8
PD
(4)
LVCMOS
gpio_129
4
IO
safe_mode
7
AE2
NA
mmc2_clk
0
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcspi3_clk
1
IO
gpio_130
4
IO
safe_mode
7
AG5
NA
mmc2_ cmd
0
IO
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcspi3_ simo
1
IO
gpio_131
4
IO
(3)
The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
(4)
The PU nominal drive strength of this IO cell is equal to 25
µA @ 1.8V and 41.6 µA @ 3.0V. The PD nominal drive strength of this IO
cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V.
TERMINAL DESCRIPTION
20
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