SPMCK16Z4MPV16 datasheet(239/500 Pages) FREESCALE

239 / 500 page

M68HC16 Z SERIES

QUEUED SERIAL MODULE

USER’S MANUAL

9-29

RDRF must be cleared before the next transfer from the shifter can take place. If

RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR)

flag in SCSR is set. OR indicates that RDR needs to be serviced faster. When OR is

set, the data in RDR is preserved, but the data in the serial shifter is lost. Because

framing, noise, and parity errors are detected while data is in the serial shifter, FE, NF,

and PF cannot occur at the same time as OR.

When the CPU16 reads SCSR and SCDR in sequence, it acquires status and data,

and also clears the status flags. Reading SCSR acquires status and arms the clearing

mechanism. Reading SCDR acquires data and clears SCSR.

When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set.

Because receiver status flags are set at the same time as RDRF, they do not have

separate interrupt enables.

9.4.3.7 Idle-Line Detection

During a typical serial transmission, frames are transmitted isochronally and no idle

time occurs between frames. Even when all the data bits in a frame are logic ones, the

start bit provides one logic zero bit-time during the frame. An idle line is a sequence of

contiguous ones equal to the current frame size. Frame size is determined by the state

of the M bit in SCCR1.

The SCI receiver has both short and long idle-line detection capability. Idle-line detec-

tion is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of

detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set.

For short idle-line detection, the receiver bit processor counts contiguous logic one bit-

times whenever they occur. Short detection provides the earliest possible recognition

of an idle line condition, because the stop bit and contiguous logic ones before and

after it are counted. For long idle-line detection, the receiver counts logic ones after

the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.

In some applications, software overhead can cause a bit-time of logic level one to oc-

cur between frames. This bit-time does not affect content, but if it occurs after a frame

of ones when short detection is enabled, the receiver flags an idle line.

When the ILIE bit in SCCR1 is set, an interrupt request is generated when the IDLE

flag is set. The flag is cleared by reading SCSR and SCDR in sequence. IDLE is not

set again until after at least one frame has been received (RDRF = 1). This prevents

an extended idle interval from causing more than one interrupt.

9.4.3.8 Receiver Wake-Up

The receiver wake-up function allows a transmitting device to direct a transmission to

a single receiver or to a group of receivers by sending an address frame at the start of

a message. Hardware activates each receiver in a system under certain conditions.

Resident software must process address information and enable or disable receiver

operation.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV16 Datasheet(PDF) 239 Page - Freescale Semiconductor, Inc

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