SPMCK16Z4MPV16 datasheet(109/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-3

5.2.2 Interrupt Arbitration

Each module that can request interrupts has an interrupt arbitration (IARB) field. Arbi-

tration between interrupt requests of the same priority is performed by serial conten-

tion between IARB field bit values. Contention will take place whenever an interrupt

request is acknowledged, even when there is only a single request pending. For an

interrupt to be serviced, the appropriate IARB field must have a non-zero value. If an

interrupt request from a module with an IARB field value of %0000 is recognized, the

CPU16 processes a spurious interrupt exception.

Because the SIM routes external interrupt requests to the CPU16, the SIM IARB field

value is used for arbitration between internal and external interrupts of the same pri-

ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all

other modules is %0000, which prevents SIM interrupts from being discarded during

initialization. Refer to 5.8 Interrupts for a discussion of interrupt arbitration.

5.2.3 Show Internal Cycles

A show cycle allows internal bus transfers to be monitored externally. The SHEN field

in SIMCR determines what the external bus interface does during internal transfer op-

erations. Table 5-1 shows whether data is driven externally, and whether external bus

arbitration can occur. Refer to 5.6.6.1 Show Cycles for more information.

5.2.4 Register Access

M68HC16 Z-series MCUs always operate at the supervisor level. The state of the

SUPV bit has no meaning.

5.2.5 Freeze Operation

The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in-

ternally by the CPU16 if a breakpoint occurs while background mode is enabled. When

FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt

timer are affected. The halt monitor and spurious interrupt monitor continue to operate

normally. Setting the freeze bus monitor (FRZBM) bit in SIMCR disables the bus mon-

itor when FREEZE is asserted. Setting the freeze software watchdog (FRZSW) bit dis-

ables the software watchdog and the periodic interrupt timer when FREEZE is

asserted.

Table 5-1 Show Cycle Enable Bits

SHEN[1:0]

Action

Show cycles disabled, external arbitration enabled

Show cycles enabled, external arbitration disabled

Show cycles enabled, external arbitration enabled

Show cycles enabled, external arbitration enabled;

internal activity is halted by a bus grant

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