SPMCK16Z4MPV16 datasheet(113/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-7

Figure 5-5 System Clock Filter Networks

The synthesizer locks when the VCO frequency is equal to fref. Lock time is affected

by the filter time constant and by the amount of difference between the two comparator

inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta-

tus is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come

out of reset until the synthesizer locks. Crystal type, characteristic frequency, and lay-

out of external oscillator circuitry affect lock time.

When the clock synthesizer is used, SYNCR determines the system clock frequency

and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-

back path, enabling frequency multiplication by a factor of up to 256. When the W or

Y values change, VCO frequency changes, and there is a VCO relock delay. The SYN-

CR X bit controls a divide-by circuit that is not in the synthesizer feedback loop. When

X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock frequency

is one-fourth the VCO frequency (fVCO). When X = 1, a divide-by-two circuit is enabled

and system clock frequency is one-half the VCO frequency (fVCO). There is no relock

delay when clock speed is changed by the X bit.

When a slow reference is used, one W bit and six Y bits are located in the PLL feed-

back path, enabling frequency multiplication by a factor of up to 256. The X bit is lo-

cated in the VCO clock output path to enable dividing the system clock frequency by

two without disturbing the PLL.

When using a slow reference, the clock frequency is determined by SYNCR bit set-

tings as follows:

The reset state of SYNCR ($3F00) results in a power-on fsys of 8.388 MHz when fref

is 32.768 kHz.

NORMAL/HIGH-STABILITY XFC CONN

1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION.

VDDSYN

0.01

µF

0.1

µF

XFC1

VSS

0.1

µF

VDDSYN

0.01

µF

0.1

µF

XFC1, 2

VSS

0.1

µF

18 k

Ω

0.01

µF

NORMAL OPERATING ENVIRONMENT

HIGH-STABILITY OPERATING ENVIRONMENT

2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE.

sys

ref Y1

() 2

()

Freescale Semiconductor, Inc.

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